The Power7 chips are implemented in a 45 nanometer copper/SOI process and have 1.2 billion transistors with eight cores on a single die.

At SC09, IBM gave out a lot more details on the four-chip multichip module (MCM) that it said it was cooking up for supercomputing customers

The picture shows the Power7 IH node MCM chip package, with the four eight-core Power7 chips. Next to it is the IH node hub/switch, which is implemented in a similar chip package.

Both chip packages have the same pin count at 5,336 pins (92 pins by 58 pins) [...]
The package has 512 GB/sec of aggregate memory bandwidth and 192 GB/sec of I/O bandwidth.

IBM now confirms that for this Power7 IH MCM, clock speeds will range from 3.5GHz to 4GHz

The Power7 IH node, as you can see in this picture, is not small. It is 39 inches wide by 6 feet deep, including space for cables. The IH node drawer is 2U high and it has room for eight of these Power7 IH MCMs, for a total of 256 cores.

The IH nodes are completely water-cooled, with water blocks on the Power7 MCM packages, on the 8 GB DDR3 memory modules IBM had specially designed for the box, and on the Power7 IH hub/switches, which were not given a proper name yet.

The water cooling links into the nodes through the front of the chassis, which is to the right in this picture. The chassis weighs a little more than 300 pounds fully loaded. A dozen of these, plus up to 1PB of local storage, can be put into a specially designed rack. This rack delivers 98.3 teraflops of number-crunching power.